1. Field of the Invention
The invention relates to integrated logic circuits, and particularly to MOS logic circuits converting TTL levels to MOS logic levels.
2. Description of the Related Art
Conventional transistor-transistor logic (TTL) to metal oxide semiconductor (MOS) converters implemented in complimentary MOS (CMOS) technology suffer from high standby currents or high through-currents or both. A cause of high standby current is when the most positive down level, or logical "0", at up to 0.8 V biases the n-channel transistor of the CMOS transistor pair to a conduct slightly when it should not. Another cause for a high standby current is when the positive voltage supply is about 0.8 V higher than the up level, or logical "1", biasing the p-channel transistor of the CMOS pair slightly on. High through-current occurs when both n-channel and p-channel transistors of the CMOS transistor pair are conducting when the TTL input signal swings from one logic level to the other. Methods to eliminate high standby currents and through-currents include adding control inputs and, thereby, circuit delays. Other methods add numerous circuit elements increasing circuit complexity and circuit delay, and requiring considerably more silicon real estate.
FIG. 1 shows a high level block diagram of such a converter, where input section 100 is connected to the gated output section 130 through terminal B and gate section 110 is connected to input section 100 through terminal A1. Input section 100 receives input 10 (IN), while both gate section 110 and gated output section 130 receive input 15 (RAS) as input. Gated input section 130 is connected to output 11 (OUT).
FIG. 2 is a detailed diagram of FIG. 1 where each numeral of FIG. 1 designates the same member in FIG. 2. Input section 100 consists of a p-channel transistor 101 and an n-channel transistor 102 connected in series between supply voltage 12 (V.sub.CC) and terminal A1. The gates of both transistors are connected to input 10 and the connection between the two transistors is terminal B. Together the two transistors form a complimentary MOS (CMOS) transistor pair. The substrate of transistor 101 is connected to the supply voltage 12 (V.sub.CC) and the substrate of transistor 102 is connected to reference potential 14 (V.sub.SS). Input 15 is connected to the gate of n-channel transistor 111 and its drain-source is connected between terminal A1 and reference potential 14.
The gated output section 130 consists of the gate transistor 134 and a Schmitt trigger 131, with transistors 132 and 133 determining the turn-on and turn-off characteristics. N-channel transistor 134 has its source-drain connected between supply voltage 12 and terminal B, its gate is connected to input 15. When input 15 goes negative transistor 134 conducts and pulls up terminal B, thus disabling output section 130. N-channel transistor 132 has its drain connected to terminal B, while source and substrate are connected to reference potential 14. The gate of transistor 132 is connected to output 11. N-channel transistor 132 starts conducting when the signal at output 11 goes up, pulling the input of Schmitt trigger 131 down, thus increasing the sensitivity of the Schmitt trigger. P-channel transistor 133 has its source-drain connected between supply voltage 12 and terminal B, and its gate to output 11. P-channel transistor 133 starts conducting when the signal at output 11 goes down, pulling the input of Schmitt trigger 131 up, making the Schmitt trigger less sensitive to signal fluctuations at its input.
A TTL-to-MOS converter is described in U.S. Pat. No. 4,437,025 (Liu et al.) which uses an enhancement mode transistor connected as a diode and a combination of depletion and enhancement mode transistors in the rest of the circuit. U.S. Pat. No. 4,568,844 (O'Connor) discloses an inverter level-shifter circuit for TTL-to-MOS interfacing, having an input stage with an active depletion and enhancement mode transistor input and a depletion mode, diode wired, load transistor. U.S. Pat. No. 5,455,520 (Honda) provides a TTL-CMOS input circuit which uses a control circuit connected to the input terminal to reduce current consumption during intermediate states of the input signal.